This invention relates to testing delay generating circuits in integrated circuits such as programmable logic device integrated circuits.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit. When the design process is complete, the tools generate configuration data files. The configuration data is loaded into memory elements on the programmable logic devices to configure the devices to perform the desired custom logic function.
During normal operation of a programmable logic device, loaded memory elements produce static output signals that are applied to the gates of metal-oxide-semiconductor (MOS) field-effect transistors (e.g., pass transistors). The memory element output signals turn some transistors on and turn other transistors off. This selective activation of certain transistors on the device customizes the operation of the device so that the device performs its intended function.
Integrated circuits such as programmable logic devices may contain adjustable delay circuitry that adds delays to signals such as clock signals. Examples of delay circuitry include phase-locked loop circuits with variable output delays and input-output blocks that contain programmable delay chains. After an integrated circuit containing delay circuitry has been designed and fabricated, it may be desirable to test the functions of the delay circuitry to ensure that the delay circuitry is providing the correct amount of delay time.
Traditional methods for testing delay circuitry on a programmable logic device may include routing signals to an external output, and using external test equipment to measure the delay time. Delay fault testing using test patterns generated by external automatic test pattern generation tools is also possible. However, these methods may be costly and may not have the precision to measure very small delays on the order of picoseconds.
It would be desirable to provide test circuitry for testing delays that is precise and cost-efficient to implement.